The present invention relates to a semiconductor device, and more particularly, to a method for fabricating contacts for improving a process margin.
As an integration degree of a semiconductor device is increased, it becomes difficult to form patterns precisely on a wafer or a semiconductor substrate. In a cell matrix region of a memory device such as a Dynamic Random Access Memory (DRAM), regularly repeated cell patterns are patterned, while in an outer cell matrix region, i.e. a peripheral region, the patterns are disposed somewhat irregularly. Accordingly, regularity of the pattern or linearity in a disposition is varied in an edge region or a boundary between the cell matrix region and the peripheral region, and a pattern defect such as a bridge is thus caused in the cell matrix edge and a loss in a process margin is generated as the result.
In a case of a landing plug contact, which is one of multiple contacts and is introduced under a bit line contact and a storage node contact, regularity in disposition is varied as it goes from a cell array to the cell matrix edge. Also, it becomes difficult to ensure a process margin in a storage node contact connected to a capacitor when a critical dimension of a contact hole for the storage node contact is formed the same as that of a storage node contact disposed in the cell array. It can be considered to form the critical dimension of the contact hole for the storage node contact adjacent to the cell matrix edge to relatively large, but in this case a self aligned contact margin with a bit line under the storage node contact can be reduced. Accordingly, a self aligned contact failure such as a short between the bit line and the storage node contact can occur. Also, when considering that a hard mask of a gate or a capping layer thereunder is lost by chemical mechanical polishing upon formation of the landing plug contact in a self aligned contact process, relative enlargement of the size of the storage node contact can cause a self aligned contact failure such as a short between the storage node contact and the gate.